There are interesting ideas in this paper from David Andrews (Kansas), Ron Sass (UNC Charlotte), Erik Anderson (ISI USC), Jason Agron, Wesley Peck, Jim Stevens, Fabrice Baijot and Ed Komp (all Kansas).
The authors advocate managing the co-operation of software and hardware in reconfigurable computers by having asynchronous software and hardware threads that interact as peers, with shared global memory. POSIX threads (pthreads) are the basis for their work, to which they have hardware threads and named the result hthreads. The authors are looking to take operating systems and middleware layer abstraction across the CPU/FPGA boundary and into the FPGA itself. Hardware threads can be created either by hand in HDL, or via the authors own C-to-VHDL tool. In this paper of January 2008, the system has been implemented on Virtex-II Pro FPGAs. At present the software threads are implemented on the PowerPC core that is on the V-II Pro die, so the entire system is on a single chip (off-chip memories notwithstanding). Future incarnations will accomodate multiple cores, and soft cores such as Microblaze for software threads. The diagram below shows an example of how the system operates in practice.
The PowerPC core is configured for the processor local bus (PLB) , and all the hthread cores and hardware threads are on the on-chip peripheral bus (OPB).
From the introduction comes this section:
[Current RC design approaches] treat the FPGA as a coprocessor on which low-level instruction- and data-level parallelism can be mapped as an extension of the execution stream running on the CPU. These approaches are concerning for the reconfigurable computing community, as lessons learned from historical parallel processing efforts clearly indicate the need to provide portable parallel programming models composed of unaltered high-level languages, operating systems, and middleware libraries]
